The present invention relates to a semiconductor integrated circuit device, more specifically to a phase compensation technique for amplifiers that the circuit device contains.
As a general trend in the semiconductor integrated circuit device, the withstanding voltage is being lowered, accompanied with the advancement of micro fabrication of MOS transistors. Accordingly, when a high supply voltage VDD is supplied from the outside, an internal supply voltage VDDI being lower than VDD is generated on the basis of the high supply voltage VDD, and the internal supply voltage VDDI is supplied to internal circuits as the operational supply voltage. Such an internal supply voltage VDDI is generated by means of a limiter circuit (named also as voltage-dropping circuit).
The limiter circuit includes a p-channel MOS transistor called a driver PMOS, and a differential amplifier that drives the driver PMOS on the basis of the comparison result of a detected voltage of the internal supply voltage VDDI and a reference voltage VREF. The high supply voltage VDD is lowered by the voltage across the source and drain of the driver PMOS, whereby the internal supply voltage VDDI is generated. When the level of the internal supply voltage VDDI is varied, the variations are reflected to the comparison result with the reference voltage VREF, and the feedback control of the internal supply voltage VDDI is carried out, whereby the voltage level of the internal supply voltage VDDI is stabilized.
In order to prevent oscillations in the circuit, the limiter circuit is provided with a phase compensation circuit. As the phase compensation circuit, the pole/zero compensation system can be quoted. The pole/zero compensation system connects a phase compensating resistor and a phase compensating capacitor in series between the internal supply voltage VDDI and a low supply voltage VSS to secure a phase margin.
As an example, Japanese Unexamined Patent Publication No. 2002-25260 discloses a semiconductor integrated circuit device in which an externally supplied voltage is let down to a lower voltage to be supplied to internal circuits.